Field Effect Transistors

1. In the previous chapter we have seen that in the bipolar transistors a small current of base controls a current of very superior collector. The transistors of field effect are triterminal devices in which the main current is controlled by means of a tension. The basic characteristicses are:
   1. The control power is null, that is to say, current by the control terminal is not absorbed.
   2. A very weak signal can control the device.
   3. The control tension is used to create an electric field.

   There are two families of transistors of field effect: the JFET and the MOSFET. Although the basic concept of the FET was known already in 1930, these devices only began to make commercially as of the decade of the 60. And from the 80 transistors of type MOSFET they have reached an enormous popularity. Compared with the BJT, transistors MOS they occupy less space, that is to say, within an integrated circuit it can incorporated I number greater. In addition its process to manufacture is also simpler. In addition, a great number of functions exists logics that can solely be implemented with transistors MOS (without resistance nor diodes). This has made of transistor MOS the component star of the digital electronics.

   In this chapter the principle of operation of both types of devices, as well as their elementary circuitales models is explained.
    

   TRANSISTOR OF EFFECT OF UNION FIELD (JFET)

   A JFET of channel N makes spreading a region of P type in a channel of N type, so and as it is in Figure 1. To both sides of the channel the terminals of source (S, S ource)anddrainage are connected (D, Drain). The third terminal denominates door (G, Gate).

   

   Figure 1: Scheme of transistor JFET of channel N

   The symbols of this type of devices are:

   

   Figure 2: Symbols of transistors JFET

   The explanations including in this chapter talk about fundamentally to transistor NJFET, considering that the principle of operation of the PJFET is analogous.

   PRINCIPLE OF OPERATION OF THE NJFET

   Next it is explained how the current in a JFET is controlled. Like the JFET happens to transistors BJT it has three regions of operation:

   • Region of cut
   • Linear region
   • Region of saturation

   It is precise to make notice that in this case, the saturation alludes to a phenomenon completely different from the one from transistors BJT.

   Region of cut

   Let us focus our attention on Figure 1. The zone of P type connected to the door forms a diode with the channel, that is of N type. As one will remember, when a union PN forms appear in the edges of same a zone of deplección in which there are no free carriers of load. The width of this zone depends on the applied polarization. If this is inverse, the zone becomes wider, proportionally to the applied tension. Applying a negative tensionV _GS we increased the width of the zone of deplección, with which the width of conduction diminishes channel N.

   If the value of V_GS becomes the sufficiently negative thing, the exhaustion region will extend completely through the channel, of which the resistance of the same one will take control infinite and the passage of I _D will be prevented (Figure 3). The potential to which east phenomenon happens denominates potential of blockade (Pinch Voltage, V_P).

   

   Figure 3: Scheme of transistor JFET of channel N polarized with the tension of blockade

   Therefore, for values more negative than V_P transistor NJFET is polarized in the cut region, and the drainage current turns out to be null.

   Linear region

   If in the structure of Figure 1 a tension V _DS is applied greater than zero, will appear a current circulating in the sense of the drainage to the source, current that we will call I_D. The value of current happiness will be limited by the resistance of conduction channel N. In this case two situations can be distinguished according to is greator small V _DS in comparison with V_GS.

   Small values of the voltage drainage-source

   Figure 4 presents/displays the situation that is obtained when union GS with a negative tension is polarized, whereas a tension between smaller D and S is applied.

   

   Figure 4: Scheme of transistor JFET of channel N polarized with V_GS < 0

   Around the terminal of door (g) it does not circulate more than the current of flight of the diode GS, that in one first approach we can consider despicable. Current I_D presents/displays one double dependency:

   • Current I_D is directly proportional to the value of V_DS
   • The width of the channel is proportional to the difference between V_GS and V_P. As I_D is limited by the resistance of the channel, whichever greater it is V_GS - V_P, greater it will be the width of the channel, and greater the obtained current.

   Both previous points take shelter in the following expression:

   

   Therefore, in the linear region we directly obtain a proportional current to V_GS and V_DS.

   High values of the voltage drainage-source

   For values of V_DS comparable and superior to V_GS the situation changes with respect to the previous case: the resistance of the channel becomes nonlinear, and the JFET loses their ohmic behavior. Let us see why this happens.

   When a voltage V _DS is applied to the channel of 5 volts, for example, this it is distributed throughout the channel, that is to say, in the proximities of terminal D the tension will be of 5 V, but halfway the circulating current will have reduced its potential to half (2.5 V), and in the terminal S the potential will be null. On the other hand, if V_GS is negative (- 2 V, for example), the tension will be distributed uniformly throughout the P zone, when not existing no current (Figure 5). (NOTE: the fall of tension in the zones located below the contacts not deigns).

   

   Figure 5: Scheme of transistor JFET of channel N polarized with V_GS = -2 5 V andV _DS = V

   Let us follow ahead. In the proximities of the terminal S the applied inverse tension is of 2 V, that corresponds with V_GS = -2 V. , nevertheless in agreement we approached D this tension increases: in half of the channel V is of 4.5, and in 7 D V reaches. The inverse polarization applied to the channel is not constant, with which the width of the zone of deplección will not be it either (Figure 6). When V_DS is small, this difference of widths does not affect to the conduction in the channel, but when it increases, the variation of the conduction section causes that the drainage current is a function nonlinear of V_DS, and that diminishes with respect to the obtained one without considering east effect.

   

   Figure 6: Scheme of transistor JFET of channel N in the region of conduction nonlinear

   Region of saturation

   If V_DS is increased more, it will be arrived at a point where the thickness of the channel in the end of the drainage approaches zero. As of that moment, the current stays independent of V_DS, since the increases of tension cause a greater narrowing of the channel, with which the global resistance increases (Figure 7).

   

   Figure 7: Scheme of transistor JFET of channel N in the region of constant current

   The saturation region occurs when the channel in the drainage strangles, which happens when the tension door-drainage is more negative than V_P, is to say:

   V_GD < V_P = > V_GS - V_DS < V_P = > V_DS > V_GS - V_P

   Before following ahead, we compare the figures 3 Figure and Figure 7. In the case of the blockade, all the channel is affected by the zone from deplección, that is constant because tension V_GS is applied uniformly throughout the union. However, in the region of constant current only part of the channel has arrived at the blockade (caused by V_DS, that varies throughout the same one), and it is what the circulation of the current allows.

   1.2 CURVED CHARACTERISTICS

   They are the two curves that are handled habitually to characterize transistors JFET. In the first place, in the representation of I_D as opposed to V_GS, for a givenV _DS, the passage of the region of cut to the one of saturation is appraised clearly (Figure 8). Actually only one operates in the second quadrant of the graph, since first positiveV _GS lets grow I _Gquickly.

   

   Figure 8: Characteristic V_GS - I_D of transistor NJFET

   In characteristic V_DS - I_D of transistor NJFET is observed the difference between the regions linear and of saturation (Figure 9). In the linear region, for a determined V_GS, the current it grows proportionally to tension V_DS. Nevertheless, this growth is attenuated until getting to be null: the value of saturation is reached, in where Ionly _D depends on V_GS.

   

   Figure 9: Characteristic V_DS - I_D of transistor NJFET

   Nótese that, according to this graph, the region of saturation of the JFET is identified with the normal active region of the bipolar transistors. Whereas in RAN the collector current only depends on the one of base, here the magnitude of control is tension V_GS. On the contrary, if the resistance of the JFET in the linear region is very small can be a certain parallelism between the regions linear of JFET and saturation of the BJT.

   1,3 COMMERCIAL PARAMETROS

   One appears next some of the characteristics of the transistors JFET that offer the manufacturers in the data sheets:

   • I_DSS: It is the drainage current when transistor JFET is in configuration of common source and cortocircuita the door and the source (V_GS= 0). Actually it marks to the Maxima intensity that can circulate around the transistor. It agrees to consider that transistors JFET present/display ample dispersions in this value.
   • V_P (Pinch-Off Voltage): it is the tension of strangling of the channel. Like I_DSS, presents/displays forts dispersions in their value.
   • R_DS(ON): He is inverse of the slope of curve I_D/V_DS in the linear zone. This value stays constant until values of V_GD near the strangling tension.
   • B_YOU (Drain-Source Breakdown Voltage): it is the tension of rupture between source and drainage. Tensions higher than B_YOU cause a fort increase of I_D.
   • B_VGS (Gate-Source Breakdown Voltage): it is the tension of rupture of the union between the door and the source, that is polarized in inverse. Greater values of B_VGS cause a conduction by avalanche of the union.

   1,4 MODELS OF TRANSISTOR NJFET

   Analogous to the carried out thing with the bipolar transistor they are going away to present/display two models for the JFET: one to analyze the operation of the transistor JFET with continuous signals and another one for the applied alternating signals on a point of operation of the saturation region.

   In the first place the models for the different regions from operation appear, that is to say, cuts, saturation and linear zone. To start off of the equations dictated by this model, the necessary expressions for the analysis of signals of alternating are deduced later of small amplitude.

   1.4.1 Ideal static model

   For transistor NJFET, the model it comes represented in Figure 10. The value of I_D depends on the operation region of the transistor.

   

   Figure 10: Circuital scheme of the model of transistor JFET

   1. Region of cut: the condition of the cut region is that the channel completely is strangled in the proximities of the source, which happens when the tension door-source reaches the strangling tension (V_GS< V_P). In this case I_D= 0.
   2. Linear region: it is the region in which an increase of intensity I _D when increasing V _DS takes place. This increase is linear for low values of V_DS although the linearity is lost when V_DS approaches - V_P. In order to work in the linear region two conditions are due to give:
   • V_GS > V_P
   • V_GD > V_P V_GS > V_P + V_DS

   These conditions are equivalent to admit that the conduction channel does not strangle as much by the zone of deplección in inverse in the end of drainage like in the source. The value that takes current I_D is

   

   1. Region of saturation: the saturation region takes place when the tension between drenador and door reaches the strangling tension. So that it happens, channel N, must be strangled in the end near the drainage, but not in the end of the channel near the source. Then, like in the previous case, two conditions must happen:
   • V_GS > V_P
   • V_GD < V_P V_GS < V_P + V_DS

   In this case intensity I_D no longer depends on V_DS, being its expression

   

   Generally, in transistors NJFET as much V_P as V_GS they take negative values, whereas V_DS and I_DSS is positive, taking direction I_D so and as it appears in the model.

   1.4.2 Model for alternating signals

   For the deduction of the same one the following hypotheses are considered:

   • Transistor polarized in the saturation region
   • Alternating oscillations of low amplitude and LF

   1.4.2.1 General expressions

   Of between the diverse possible options, for the deduction of the model tensions V _GS and V _DS are chosenlike independent variables, whereas the employees are currents I_G and I_D. This way, the equations characteristic of the transistor will come given by two functions f₁ and f₂ such that:

   

   The tensions and currents of a concrete point of polarization will come given by the previous expressions:

   

   Let us suppose that on this point of operation Q an alternating component is added, characterized by a V_GS and a V_DS. The oscillations of the currents can calculate like:

   

   As of this moment, to simplify the annotation the increases of the variables will be written with very small letter. The previous expression admits a matrix representation:

   

   in where the coefficients and_ij are called parameters admittance.

   • and_is : Admittance of entrance (^-1)
   • and_RS: Admittance of inverse transference (^-1)
   • and_fs : Transconductancia (^-1). Usually one names like g_m
   • and_you : Admittance of exit (^-1)

   1.4.2.2 Calculation of the parameters admittance

   For the calculation of the parameters and_ij they are going away to use the resulting expressions of the static model for the saturation region.

   • Function f₁ = >
   • Function f₂ = >

   

   

   The circuital representation of this simplified model responds to the same scheme presented/displayed in Figure 10.

   2 TRANSISTOR MOSFET

   The benefits of transistor MOSFET are similar to those of the JFET, although their principle of operation and its internal structure are different. Four types of transistors MOS exist:

   • Enrichment of channel N
   • Enrichment of P channel
   • Impoverishment of channel N
   • Impoverishment of P channel

   The symbols are:

   

   

   Figure 11: Transistors MOSFET

   The common constructive characteristic to all the types of transistor MOS is that the terminal of door (g) is formed by a structure of Metal/Óxido/Semiconductor type. The oxide is insulating, with which the door current is practically null, much smaller than in the JFET. For that reason, the MOS is used to deal with signals very low power.

   2,1 OPERATION PRINCIPLE

   Of between all the types of existing transistors MOS one is going away to analyze the principle of operation of two of them: the NMOS of enrichment and impoverishment.

   2.1.1 NMOS of enrichment

   In Figure 12 the scheme of a MOS of enrichment appears channel N.

   

   Figure 12: Scheme of enrichment transistor NMOS

   Let us suppose that a tension V _DS is applied greater than zero whereas V_GS stays in zero. When applying a positive tension to zone N of the drainage, the diode that forms this one with the P substrate will polarize in inverse, with which the current passage will not be allowed: the MOS will be in cut.

   Let us continue supposing, and we think now that we applied a positive potentialV _GS, while we also maintain V _DS positive. The layer of insulator of the door is very thin, as much that it allows the positive potential applied to repel to the hollows and to attract electrons of the P. material To greater applied potential, greater number of electrons will be attracted, and greater number of hollows repelled. The consequence of this movement of loads is that underneath the terminal G a negative channel is created, of N type, that puts in contact the drainage with the source. Around this channel a current can circulate. Summarizing, over a positive value V_GS = V_TH makes possible the circulation of current I_D (Figure 13). We were before a region of linear conduction.

   

   Figure 13: Scheme of transistor NMOS of enrichment in conduction

   If the value of V_DS increases, the effective tension on the channel in the proximities of the drainage (V_GS - V_DS) is diminishing, with which the channel is narrowed in this zone, and the linearity in relation I _D is lost - V_DS. Finally it is arrived at a situation of saturation similar to which is obtained in the case of the JFET.

   2.1.2 NMOS of impoverishment

   In Figure 14 the scheme of a MOS of impoverishment appears channel N.

   

   Figure 14: Scheme of impoverishment transistor NMOS

   In this case the channel already is created. Therefore, if with V_GS = 0 we applied a tension V_DS will appear a current of drainage I_D. So that the transistor happens to the cut state will be necessary to apply a tension V_GS smaller than zero, than it expels to electrons of the channel.

   

   Figure 15: Scheme of transistor NMOS of impoverishment in cut

   Also in this case, the application of a V_DS much greater than V_GS causes a situation of independendiente current of V_DS.

   2.2 CURVED CHARACTERISTICS

   With transistors MOS two types of graphs are handled: characteristic V_GS - I_D, with constantV _DS, and V_DS - I_D with constantV _GS.

   2.2.1 Transistor NMOS of enrichment

   

   Figure 16: Characteristic V_GS - I_D of enrichment transistor NMOS

   In Figure 16 it is shown how intensity I_D increases abruptly when surpasses the tension threshold V_TH (Threshold Voltage) and the channel is created. It is a suitable component for commutation, since it happens of a cut state to one of conduction from a value of the control signal. In the devices with the terminal of aluminum door and the silicon oxide insulator, the tension threshold is around the five volts.

   

   Figure 17: Characteristic V_DS - I_D of enrichment transistor NMOS

   Characteristic V_DS - I_D of enrichment transistor NMOS is very similar to the one of the JFET, but the values of V_GS change: in this case the conduction occurs for positive voltages over the threshold.

   2.2.2 Transistor NMOS of impoverishment

   

   Figure 18: Characteristic V_GS - I_D of enrichment transistor NMOS

   The NMOS of impoverishment can also work like enrichment transistor. If tension V_GS becomes positive they will attract electrons the channel. In addition, unlike the JFET, the impedance of continuous entrance very being elevated.

   

   Figure 19: Characteristic V_DS - I_D of impoverishment transistor NMOS

   2,3 COMMERCIAL PARAMETROS

   The more important commercial parameters of transistor MOS are analogous to those of the JFET presented/displayed in section 1.3.

   2,4 MODELS CIRCUITALES

   So and as it has been seen, the curves of operation of transistors MOS are similar to those of the JFET. For that reason, all admit an analogous circuital representation.

   2.4.1 Static model of Schichman-Hodges

   The static model of transistor MOSFET denominates model of Schichman-Hodges. It is a model very similar to the model of transistors JFET, described previously. The equivalent circuit is made up of an open switch and a source of intensity (Figure 20) whose value I_D depends on the operation region of the transistor.

   

   Figure 20: Model of Schichman-Hodges for transistor FETMOS

   For enrichment transistor NMOS the operation regions are:

   1. Region of cut
   • Condition V_GS< V_TH
   • Intensity I_D= 0
   1. Linear region.
   • Conditions: V_GS> V_TH

   V_GD < V_TH V_GS < V_TH+V_DS

   • Intensity:

   Where K is a constant that depends on the material and the dimensions of the transistor

   

   • m_and is the mobility of the electrons, that depends on the material and the temperature
   • W, Ls are the width and the length of the channel. Geometric factors that depend on the design of the transistor.
   • C'_OX is the capacity by unit of surface of the condenser that forms the metal of the door with the channel. It depends strongly on the thickness of door oxide.
   1. Region of saturation
   • Conditions V_GS > V_TH

   V_GD > V_TH V_GS > V_TH+V_DS

   • Intensity:

   2.4.2 Model for alternating signals

   For the case in which the transistor has supported to alternating signals of small amplitude and LF on a point of polarization in saturation region, it can be demonstrated of analogous form to since it has been made for the transistor JFET that transconductancia g_m calculates through the following expression

   

   3 APPLICATIONS OF THE TRANSISTORS OF FIELD EFFECT

   The general applications of all the FET are:

   3,1 ELECTRONICA ANALOGICA

   For these applications of they use prepared transistors to lead great currents and to support high tensions in cut state.

   • Variable resistors of governable value by tension (varying the width of the channel).
   • Amplifiers of tension, specially in the initial amplification of signals of very low power.
   • Control of electrical power given one loads.

   In the case of the amplification the circuits are designed so that the point of operation DC of the MOS is in the saturation region. This way a current of dependent drainage only of tension V _GS is obtained.

   3,2 DIGITAL ELECTRONICA

   The MOS is often used in digital electronics, due to the capacity to work between two states differentiated (cuts and conduction) and to his under consumption from control power. For this application devices of very low resistance are used, ideally so that it can be considered that:

   • The fall of tension in conduction is very small.
   • The transition between the state of cut and the one of conduction is instantaneous.

    
    
    

   1. In a transistor NJFET with I_DSS= 10mA and V_P = - 5 V is moderate an intensity of drainage I_D = 1mA. To find how much it is worth tension V_GS if one admits that it works in the saturation region. To find the tension of feeding and minim so that the transistor works in saturation.

   

   1. In the circuit of the figure, it is requested:

   1. - Tension V_GS if one admits that the transistor is in saturation.

   2. - If V_IN = 5V, to calculate whichever bond V_DS.

   Data of the transistor: I_DSS = 5mA; V_P= - 3V
    

   

   1. Be the circuit of the figure formed by a transistor NJFET and a resistance. It is requested:

   1. - To indicate the region of operation of the transistor.

   2. - To calculate the point of operation of the transistor.

   3. - If 1k changes to the resistance by another one of value, to find the new point of operation of the transistor.

   Data of the transistor: I_DSS = 2mA; V_P= - 3V

   

   1. Transistor NJFET of the figure has an I_DSS= 12mA and V_P= - 4V. To determine the minimum value of and so that the transitor works in the saturation region.

   

   1. To calculate the values of V_DS and V_GS of the transistor of the figure if I _D is admittedthat= 5mA.

   

   1. To determine the point of operation of transistor FET of the figure supposing that one is in zone of saturation.

   Data: I_DSS= 5mA V_P= - 4V

   

   1. To find the point of operation of the transistor of the figure. Data: I_DSS= 15mA; V_P= - 10V

   

   1. In the circuit of the figure, to calculate the resistance of entrance R_IN and the tension of exit V_OUT. If a resistance of 4.7k of the circuit is connected when coming out, to calculate the exit tension. Data of the transistor: I_DSS= 8mA, V_P= - 10V

   

   1. In the circuit of the figure a transistor has been used 2N5460. To calculate the gain of tension of the circuit. Note: To use for it the average values of the parameters of the transistor.

   

   1. To determine the gain of tension of the circuit of the figure. Data of the transistor: g_m= 3,8 mmhos

   

   1. The simple circuit of the figure is a current source that feeds a load R_L.

   a) Calcúlese the value of the current I that circulates around that load if the transistor is in the saturation region.

   b) To find the resistance R_L Maxima that can be fed with the intensity found by means of the previous circuit

   If transistor JFET of the figure is a commercial transistor 2N5486, to calculate between what values can be hoped that it varies intensity I when the transistor works in the saturation region. Data: I_dss= 10mA; V_P= - 5V.

   

   1. With the transistor 2N5457 and other components that create necessary, designs a source of constant current of 0.2mA. Which will be the fully factored load that can feed the source on current?
   1. In the circuit of the figure, to calculate the exit tension if the entrance tension is 3V. To consider that the transistor works in the saturation region. Additional data: R=100K; E=15V

   

   1. The tension of entrance V_in is a tension that varies very slowly with time so that, the circuit by means of an analysis in continuous can be solved. If E=10V and I_D= 1mA, to calculate the relation between V_out and V_in. What intensity I_D is due to establish in the source if V is wanted that_out= V_in? Data of the transistor: I_DSS= 3mA V_P= - 5V

   

   1. In the circuit of the figure, if both transistors are identical and are thermally connections. To find the relation between V_OUT and V_IN.

   

   1. To determine the value of ₀₁ exitsV and V₀₂ when V_IN is worth zero and ten volts. Data: 5V _TH = 20 V.And _CC = V.

   

   1. For the design of an investing logical door, a scheme is made like which it imagines next.

   

   a) Approximately to calculate the power generated in the source of 8 Volts in the logical states ' 1' and ' 0 ' of the entrance (10 V. and 0 V. Respectivamente).

   b) What mission has the resistance of 15 k.

   1. The following logic circuit is designed according to technique CMOS (Complementary-MOS).

   It is denominated thus so that it uses in the same circuit transistors NMOS and PMOS.

   

   a) To explain its operation and to determine what type of logical door is.

   b) To compare this circuit with the one of the previous one. What advantages present/display as far as power consumption.

   1. To select the most appropriate transistor for the following logic circuit (0 < V_IN < 10V) (To calculate the commercial parameters of the transistor):

   

   1. To determine to what type of logical door corresponds the devices of the figure (Entered: V₁ and V₂; Exit: V_Or)

   

   What power consumption has in states logical ' 1 ' and ' 0 ' of both circuits?

   1. The circuit of the figure represents a transistor acting like a switch. When the door with a tension of 15V is polarized, the transistor lets pass a current to feed the resistance on load. When polarizing with 0V the door, the transistor remains in cut. It is requested:

   a) To choose an suitable transistor MOS to make this function.

   b) Approximately to calculate the power loss in the transistor if the entrance signal is included/understood between 0 and 5V.

   

   1. A deplección transistor NMOS has a V_P= - 2V and K=2mA/V². To calculate minimumV _DS to operate in the saturation region if V_GS= 1V.
   2. Transistor MOSFET of deplección of the figure has ^{a 2}K=4mA/V and V_P= - 2V. To calculate the tension of the source

   

   1. To calculate the parameters that take resistance R_D and R_S from the circuit of the figure so that the transistor operates with an I_D= 0.4mA and V1.Datos_D =: V_TH= 2V; K=0.4mA/V²

   

   1. It is desired to design an alarm circuit for a car so that when leaving the car with the ignited lights, it sounds a buzzer. In order to detect the opening of the door one has a magnetic sensor between the door and the car that is closed with the door and signals of 0V. When opening the door, the sensor signals of 5V. On the other hand, a device is had that detects the passage of current in the circuit of illumination. A signal of 5V with the ignited lights and 0V with the dull lights is obtained. The buzzer must be fed between 1 and 16V and to receive a current of 30mA. Design the circuit with necessary transistors MOSFET.

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